1. Field of the Invention
The present invention relates generally to improved techniques for fabricating IC (integrated circuit) memory devices, and more specifically to an input interface level determiner which is provided in a memory device and eliminates the need for permanently determining memory's input interface levels during IC fabricating steps.
2. Description of the Related Art
It is known in the art that LVTTL (low voltage transistor-transistor logic) is commonly used to define voltage levels recognizable by memory devices. DRAMs (dynamic random access memories accept and provide data at LVTTL levels. Input buffers or receivers, which are provided in DRAMS and supplied with these levels, should recognize whether a voltage is intended to be a high or a low voltage. According to the LVTTL specifications, all voltages higher than 2.0 volts (viz., Voltage Input High min (VIH min)) are determined as a high voltage, and all voltages lower than 0.8 volts (Voltage Input Low Max (VIL max)) are recognized as a low voltage.
Recently, an SSTL (stub series terminated logic) specification or standard has been developed particularly with the objective of providing a relatively simple upgrade path from LVTTL designs. The SSTL specification is particularly intended to improve operations in situations where busses must be isolated from relatively large stubs. In order to operate a memory cell at SSTL levels, it is necessary for a user to determine a reference level VREF (usually around 1.5 volts). Generally speaking, the SSTL specification dictates that all voltages higher than (VREF+0.4) volts are determined as a high voltage, and all voltages lower than (VREF-0.4) volts are recognized as a low voltage. It should be noted that the above-mentioned values of .+-.0.4 volts may slightly change depending on circuit designs (for example). The SSTL standard has been provided in detail in a paper entitled "Stub Series Terminated Logic for 3.3 Volts (SSTL.sub.-- 3)" published by Standard of Electronic Industries Association of Japan, March 1996.
By way of example, the LVTTL may be used for memory devices operating up to about 100 MHz, while the SSTL is used for memory devices whose operating frequencies range above 100 MHz. This may be resulted from the fact that the voltage swing of SSTL (about 0.8 volts) is much narrower than that of LVTTL ( about 2.0 volts). It is understood that the performance characteristics of the memory devices operating at SSTL levels are stricter than those of the devices operating at LVTTL levels.
Before turning to the present invention it is deemed advantageous to briefly describe, with reference to FIG. 1, a conventional technique which may be relevant to the present invention.
As shown in FIG. 1, an interface level determiner 10 is comprised of a fuse 12 and a connection controller 14. The fuse 12 is provided between a power source line Vcc and the input terminal of the controller 14. It is assumed that when a memory chip, equipped with the interface level determiner 10, is intended to be used at SSTL levels, the fuse 12 is not broken in order to apply the power source voltage (Vcc) to the controller 14. That is to say, a high logic level (viz., Vcc) applied to the connection controller 14 indicates that the memory chip in question is to operate at LVTTL levels, the fuse 12 is destroyed, at a suitable IC fabricating step, so as to open the input terminal of the controller 14. The memory device users are informed, from the chip manufacturers, as to whether the memory device should be used at SSTL levels or LVTTL levels. In the above, it is understood that the fuse 12 can be replaced by a wire which is omitted in the case of LVTTL mode.
When the memory chip dedicated to SSTL levels is used, a reference voltage VREF is applied to an external terminal 16. The connection controller 14, which typically takes the form of a transfer gate, is responsive to the high logic level (viz., Vcc) through the fuse 12 and relays or transfer the reference voltage VREF to an input buffer 18 which typically takes the form of a differential transistor pair. Thus, the voltages applied to the buffer 18 via a data input pin 20 are recognized as a high or a low logic level using the reference voltage VREF (viz., at SSTL levels) as mentioned above.
On the other hand, in the case where the memory chip operating at LVTTL levels is used, the connection controller 14 is supplied with no input through the fuse 12 and thus does not work as a transfer gate. In this case, to be safe, no voltage is applied to the pin 16. Since the input buffer (viz., differential transistor pair) 16 recognizes the voltages applied to the data pin 20 at LVTTL levels.
As mentioned above, the memory devices operating at SSTL or LVTTL levels are permanently or uniquely determined during the IC fabricating steps, after which the performance characteristics of the devices are implemented. Let us consider the case where a given device dedicated to SSTL mode is found unsuitable for SSTL mode but usable at LVTTL levels. In this instance, it is practically impossible to change the interface mode of the device with the result of lowering the yield of the good devices.